Sampling, digital control and implementation constraints

Follow acquisition through application

Let sample index k identify an observation at time kT, where T is the nominal sample interval. A zero-order hold keeps an input constant until the next update. Acquisition, filtering, communication, calculation and output application may each contribute latency. Timestamping the message arrival cannot by itself reveal when the sensor acquired the physical quantity.

Sampling frequency is 1/T. Aliasing can make high-frequency input or noise look like a lower-frequency component. An appropriate analogue filtering and acquisition arrangement precedes sampling; digital filtering after aliasing cannot recover the lost distinction. A sampling theorem condition for representing a bounded spectrum is not a complete rule for selecting a feedback controller’s update rate.

Derive the update for a stated hold assumption

A difference equation relates states at successive updates. For the ideal integrator dx/dt=u, if u[k] is constant over the whole interval, x[k+1]=x[k]+Tu[k] follows exactly. This is not a numerical approximation for that particular hold and plant. Substituting sampled feedback u[k]=−Kx[k] gives x[k+1]=(1−KT)x[k].

The homogeneous samples decay when the multiplier’s magnitude is below one. With positive K, that requires 0<KT<2. A negative multiplier gives alternating signs, and magnitude above one gives growing sampled deviations. Extra computation delay changes the equation; a result derived for immediate application cannot silently be used for a one-sample-late implementation.

Check the timing and arithmetic actually delivered

A nominal interval is not proof of a bounded worst-case interval. Jitter, missed updates and scheduling interference can change the effective loop. Numerical rounding, quantization and overflow can alter small signals or stored integral values. Record units, ranges, saturation rules and behaviour when data are invalid rather than relying on a successful compilation.

Implementation checking includes sensor-to-output timing and the relation between the intended equation and actual update order. Simulations should represent the hold, delay, limits and chosen discretization. Refining a simulation step tests numerical sensitivity; it does not demonstrate that the physical controller meets its deadline or that its plant model is valid.

An exact sampled integrator with two intervals

Take K=1/s and x[0]=1 mm. With T=0.5 s, multiplier 0.5 gives successive positions 1, .5, .25, .125 mm. With T=2.5 s, multiplier−1.5 gives 1, −1.5, 2.25, −3.375 mm and eventually 11.391 mm at k=6. The continuous feedback law dx/dt=−x would instead decay monotonically.

The plot compares update index, so its two series represent different elapsed times. The connecting lines guide the eye; they are not the held-input system’s actual intersample trajectories. The interval choices illustrate stability, not permissible rates for any equipment.

Try the reasoning

1. At KT=2, do the samples decay?

   Show the answer and reasoning

   No. The multiplier is−1, so they alternate at constant magnitude in the ideal model. This does not provide asymptotic stability or a robustness allowance.

2. What phase lag does 20 ms pure delay add at 2 Hz?

   Show the answer and reasoning

   360×2×.020=14.4° of lag. The same delay has a larger phase effect at higher frequency.

3. Can this example establish a universal samples-per-cycle rule?

   Show the answer and reasoning

   No. Its condition follows from one integrator, held proportional input and immediate update. Other dynamics, delay and requirements change the analysis.

What to carry forward

Derive and check the implemented sequence, including the times between observations and actions.