GLOBAL KNOWLEDGE ARK

Engineering & Technology · Electrical Power, Conversion & Machines

Power electronics, switching and conversion losses

An ideal switch has either zero voltage across it or zero current through it, suggesting zero dissipation in its steady states. Real switching takes time and real conducting paths have losses. A converter therefore needs both an energy-transfer model and a thermal account.

Electrical Circuits supplies current/voltage, power, rms, phase and ideal storage relations. Engineering Thermodynamics supplies energy balances, losses and system boundaries. This chapter introduces magnetic flux and pole count before using them, derives the simple machine/converter relations and labels every invented parameter. All diagrams and numerical cases are original teaching models. They do not specify equipment construction, protective settings, installation, switching or qualification.

Back to the chapter

After reading, you can

Explain switched conversion through state intervals, stored energy and losses rather than treating duty cycle as an unconditional voltage rule.

01

Name the source and output form

Rectifiers convert AC input to DC output; inverters produce AC from DC; DC–DC converters change DC terminal relationships. Their topology, storage elements and control determine permitted voltage/current directions, isolation and response. An inverter does not create the primary energy it delivers.

Switches steer current through different circuit states. Inductors and capacitors exchange energy during those states, while a controller changes timing in response to the intended output and constraints. Faster switching does not remove charge balance, voltage stress or stored energy. A stopped control signal is also not proof that every topology has disconnected input from output.

02

Locate the current path in each switching state

Use the conceptual nonisolated buck topology in the new diagram. Source negative is the common node N, chosen as zero volts. A controlled switch connects source positive P to node A. An inductor runs from A to output node B, and a capacitor and load are connected in parallel between B and N. A freewheel diode is connected to allow current from N toward A, while blocking the opposite direction. Here the diode is an ideal one-way conducting element; its conducting voltage drop and switching transients are omitted.

Reference positive inductor current from A to B, and define its passive voltage as vL=VA−VB. When the controlled switch is on, A is at Vin. The positive A potential reverse-biases the diode, so current travels from the source through the switch and inductor to the output network, then returns to source negative. The inductor voltage is Vin−Vout. With Vin above Vout, diL/dt=vL/L is positive and the magnetic store gains energy during this interval.

When the controlled switch opens, inductor current cannot instantly stop in this finite-voltage model. The ideal diode supplies a different closed path: N through the diode to A, then through the inductor and output network back to N. The conducting diode sets VA=0, while the output capacitor keeps VB approximately at Vout over the short interval. Hence vL=0−Vout. The current still goes from A to B but decreases: a negative current slope is not a reversal of current. The inductor can now release magnetic energy to the output.

The capacitor allows inductor current and load current to differ instant by instant. In periodic steady state, its average charge change is zero, so average inductor current equals average load current when those are the only output branches. Together with the inductor returning to its initial current each period, this makes the following duty balance physically meaningful. Startup, a load step or an interval in which the diode current reaches zero needs another account; a new duty ratio does not instantaneously impose a new capacitor voltage.

Buck on and freewheel current pathsTwo ideal buck states use N=0 V, P=24 V and approximately fixed B=9 V. On: the source-to-A switch conducts, A=24 V and the N-to-A diode blocks; positive current flows A through L to B, giving vL=15 V. Off: the switch opens, the diode conducts from N to A, setting A=0 V; current still flows A to B through L and returns through the output network, giving vL=−9 V. The box represents parallel output capacitor and load. These are conceptual current paths, not a hardware schematic.A continuous inductor current uses two different return pathsIdeal positive-current buck; C and load are parallel in the output boxON: source supplies the output and raises iL24 VS closedLC ∥ loadB → NDblockedA = 24 VB ≈ 9 VN = 0 VvL = +15 ViL stays A → BOFF: freewheel path lets iL continue while falling24 VS openLC ∥ loadB → NDN → AA = 0 VB ≈ 9 VN = 0 VvL = −9 ViL stays A → BvL = VA − VB; diL/dt = vL/L; current sign and slope are differentOriginal 24 V-to-9 V state: D = 0.375; no device drops or switching transients
Two ideal buck states use N=0 V, P=24 V and approximately fixed B=9 V. On: the source-to-A switch conducts, A=24 V and the N-to-A diode blocks; positive current flows A through L to B, giving vL=15 V. Off: the switch opens, the diode conducts from N to A, setting A=0 V; current still flows A to B through L and returns through the output network, giving vL=−9 V. The box represents parallel output capacitor and load. These are conceptual current paths, not a hardware schematic.
03

Derive the duty relation from an inductor account

For an ideal buck model with positive continuous inductor current and nearly constant output voltage, the inductor sees Vin−Vout during the on interval and −Vout during the complementary freewheel interval. In periodic steady state its current returns to the same value each cycle, so average inductor voltage is zero.

If duty fraction D is on time divided by period, D(Vin−Vout)+(1−D)(−Vout)=0, giving Vout=D Vin. This result uses the stated ideal states and continuous-conduction condition. Discontinuous operation, device drops, resistances, timing limits and control behaviour can change the relation. The figure plots actual interval slopes for our declared model, not a bench trace or switching recipe.

Balanced interval voltage gives a returning current stateTime 0–200 μs at 2.7 units/μs. Voltage 15 V during first 37.5 μs of each 100 μs period and−9 V otherwise; vertical 6 units/V. Current starts 1.71875 A, rises by 0.5625 A to 2.28125 A during on interval, falls to 1.71875 A over remaining 62.5 μs, then repeats; current axis 1.5–2.5 A at 180 units/A. Average 2 A. Ideal constant 9 V output,1 mH inductor; switched output stage and losses not depicted as a physical build.Original ideal buck: 24 V → 9 V, L = 1 mH, fs = 10 kHz-9015Inductor voltage (V)1.522.5Inductor current (A)050100150200Time (μs)On time 37.5 μs per 100 μs; positive current returns each cycle.
Time 0–200 μs at 2.7 units/μs. Voltage 15 V during first 37.5 μs of each 100 μs period and−9 V otherwise; vertical 6 units/V. Current starts 1.71875 A, rises by 0.5625 A to 2.28125 A during on interval, falls to 1.71875 A over remaining 62.5 μs, then repeats; current axis 1.5–2.5 A at 180 units/A. Average 2 A. Ideal constant 9 V output,1 mH inductor; switched output stage and losses not depicted as a physical build.
04

Keep per-cycle energy distinct from average power

Conduction losses include current flowing through finite on-resistance or device drops. During transitions, voltage and current can overlap; parasitic charge movement and gate driving add other contributions. If the same total transition energy Ecycle is dissipated every switching cycle, average switching loss is Ecycle fs. That assumption may change with voltage, current and temperature.

Thermal performance depends on total losses and paths to the surroundings, not efficiency alone. A high-power converter can have high percentage efficiency and still dissipate substantial heat. Ripple, response, interference, size and losses interact, so there is no universal best switching frequency.

A converter model should retain startup, current limits, component saturation, stability, fault response and bidirectional capability when they matter to the question. The steady average relation is a useful first step, but it does not qualify a layout, controller or power stage.

Check an original periodic state and a separate loss budget

Choose ideal Vin=24 V, Vout=9 V, L=1 mH and fs=10 kHz. Then D=9/24=0.375 and period is 100 μs. During 37.5 μs on time, current rises by (15/0.001)×37.5×10⁻⁶=0.5625 A. During 62.5 μs off time it falls by (9/0.001)×62.5×10⁻⁶=0.5625 A.

With assumed mean inductor current 2 A, the triangular range is 1.71875–2.28125 A, remaining positive as required by this model. Average output power is 18 W. Ideal average input current is 18/24=0.75 A, distinct from the 2 A output current.

For a separate explicitly hypothetical loss account at 18 W output, assume conduction 0.4 W, other losses 0.2 W and transition energy 20 μJ per complete cycle. At 10 kHz, transition loss is 0.2 W and total loss 0.8 W, giving efficiency 18/18.8≈95.7%. If only switching frequency doubles with that same Ecycle, total loss becomes 1 W and efficiency 18/19≈94.7%. This isolates an assumption, not the complete prediction of a redesigned converter.

Change the ideal input to 18 V while retaining a desired 9 V output, 1 mH inductance, 10 kHz switching and an imposed 2 A mean output current. Under the same positive-current periodic assumptions, D=9/18=0.5. Node A is 18 V during the 50 μs on interval and 0 V during the 50 μs freewheel interval. Thus vL is +9 V and −9 V, respectively; current rises and falls by 9/0.001×50×10⁻⁶=0.45 A. Its triangular range is 1.775–2.225 A, so it remains positive.

Ideal output power remains 18 W, while average input current becomes 18/18=1 A. If duty were left at the old 0.375, the relation would instead predict a 6.75 V periodic steady output at 18 V input, only if that new state and conduction assumptions were established. It would not describe the first instant after the input changed or prove that a real controller maintained either target.

Try the reasoning

  1. Why must average inductor voltage be zero in this periodic ideal case?

    Show the answer and reasoning

    Otherwise its current would change from cycle to cycle rather than return to the same state.

  2. Is output current necessarily equal to average input current?

    Show the answer and reasoning

    No. Conversion changes the voltage/current relationship while the power account includes transferred power and losses.

  3. Does Vout=D Vin apply without checking conduction mode and topology?

    Show the answer and reasoning

    No. It was derived for specified ideal buck states and a positive continuous current with periodic steady behaviour.

  4. In the off interval, vL is negative. A learner therefore reverses the current arrow from B to A. Why is that inference wrong?

    Show the answer and reasoning

    The equation vL=L diL/dt sets the rate of change, not the sign of the existing current. In the illustrated positive continuous current case, current remains A to B while decreasing; the freewheel path allows that continuity.

  5. For a separate ideal 18 V-to-6 V positive-current buck state with L=1 mH and 100 μs period, find duty and the two current changes.

    Show the answer and reasoning

    D=1/3. During about 33.333 μs, vL=18−6=12 V and current rises 12/0.001×33.333×10⁻⁶≈0.4 A. During about 66.667 μs, vL=−6 V and it falls by the same 0.4 A. This closes the inductor state only if the assumed conduction mode is retained.

  6. Why does the diode-only topology need a revised state description if the inductor current reaches zero before the next on interval?

    Show the answer and reasoning

    The diode cannot support a continuing negative current under its declared one-way rule. It stops conducting, creating a third interval with different node constraints. The two-state continuous-current derivation no longer applies unchanged.

What to carry forward

Derive conversion from the state intervals, then add losses and relevant dynamic constraints.

References

Teaching resources and research supporting this lesson’s explanations and examples.

  1. SLVAFJ5 — Buck, Boost, and Buck-Boost topology discussion (March 2023)Texas InstrumentsTeaching resourceti.comRead source
  2. How the Switching Frequency Affects the Performance of Buck Converter, SLVAED3AHenry Xie and Eric Guo; Texas InstrumentsTeaching resource · PDFti.comRead source
  3. Understanding Buck Power Stages in Switchmode Power Supplies, SLVA057 (March 1999), selected state-path explanationEverett Rogers; Texas InstrumentsTeaching resource · PDFti.comRead source