Engineering & Technology · Electronics, Devices & Signal Processing

Logic circuits, timing and digital interfaces

A truth table can be correct while a receiving register stores the wrong value. Logic meaning, voltage compatibility and arrival time are separate parts of the same interface. A digital abstraction becomes useful when those physical conditions are controlled.

Electrical Circuits supplies charge/current balance, stored energy, sinusoidal phase, rms and the unloaded RC response. Material Structure & Properties supplies the distinction between a material description and a complete product. This chapter explains bias and feedback before using gain. It introduces spectra through an explicit two-tone sum and sampling through points on known curves. All parameters, code intervals, timing values and noise examples are original teaching models; no physical construction or performance qualification is implied.

Back to the chapter

After reading, you can

Connect Boolean functions to physical interface levels and timed storage without treating digital signals as ideal instantaneous voltages.

State what the bits mean

For a simple illustrative alarm, let A mean “request present” and B mean “inhibit present”. Define output Y=A AND NOT B. The four input pairs 00, 01, 10 and 11 then give 0, 0, 1 and 0. This is an invented logical requirement, not a safety-rated alarm design.

Combinational logic gives an output function of current inputs after propagation. Sequential logic includes stored state. A rising-edge D register is modelled as capturing its D input near an active clock transition and presenting that stored bit at Q after a delay. A clock symbol does not make an input arriving at any time acceptable.

Compare guaranteed ranges under the same conditions

A physical logic 1 occupies an allowed voltage range, not one mathematically exact voltage. A hypothetical driver guarantees output high at least 2.9 V and low at most 0.3 V under stated loading. A hypothetical receiver requires high at least 2.0 V and low at most 0.8 V. The static high and low noise margins are 0.9 V and 0.5 V respectively.

These invented values illustrate comparisons, not a universal logic-family interface. Supply range, output current, input tolerance, rise/fall time, return path, capacitance and powered/unpowered states still matter. A voltage between accepted high and low ranges has no guaranteed ordinary logic interpretation merely because it falls nearer one label.

Preserve a stable value around capture

Setup time requires an input to be stable before the specified clock event; hold time requires it to remain stable afterward. A violation can leave the stored result uncertain or delay resolution. It is not a reliable way to choose which bit wins.

For a register-to-register path, check the slow path against the next setup deadline and the fast path against hold. Longer clock periods can help a slow setup path, but they do not automatically fix a too-fast hold path associated with the same edge. Real analysis also includes clock skew, jitter and variations. Our figure deliberately assumes one aligned clock and exact model delays to teach the two comparisons.

Time 0–10 ns at 52 units/ns. Rising clock edges at 0 and 10 ns. Launch plus logic minimum delay 0.5+1=1.5 ns; maximum 2+5=7 ns, shown orange. Receiver hold deadline 1 ns and next setup deadline 10−1=9 ns. Earliest data satisfies hold by 0.5 ns; latest data satisfies setup by 2 ns. This exact simplified model omits skew, jitter and parameter variation; no physical timing qualification.

Check both ends of a path delay range

In an original model, the launching register changes Q no earlier than 0.5 ns and no later than 2 ns after the clock. Logic delay ranges from 1 ns to 5 ns. The receiving register needs setup 1 ns and hold 1 ns. Ignore skew and jitter only for this calculation.

The latest new data arrives at 2+5=7 ns. It must arrive at least 1 ns before the next edge, so the clock period must be at least 8 ns in this exact simplified model. At 10 ns, the nominal setup slack is 10−(2+5+1)=2 ns. This alone is not a real maximum-frequency specification.

The earliest change arrives at 0.5+1=1.5 ns, later than the 1 ns hold boundary, leaving 0.5 ns in this model. If the logic minimum were zero, the earliest change would be 0.5 ns and hold would fail even with a very long period. Timing needs both minimum and maximum path information.

Try the reasoning

Does a correct truth table establish that a connected physical receiver will work?
Show the answer and reasoning
No. Voltage levels, loading and timing must also be compatible.
Why can lowering clock frequency leave a hold violation unresolved?
Show the answer and reasoning
The earliest new-data change relative to the same capture edge may remain too early.
Do the 0.9 V and 0.5 V margins prove immunity to every disturbance?
Show the answer and reasoning
No. They compare specified static levels under their assumed conditions; transient, reference and loading effects require their own checks.

What to carry forward

A bit travels through a physical interface. Check meaning, levels, slow arrival and fast arrival separately.

References

Teaching resources and research supporting this lesson’s explanations and examples.