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Engineering & Technology · Instrumentation, Sensors & Embedded Integration

Data acquisition, timing and measurement synchronisation

Two sensors connected to one acquisition device can appear in the same row of a file without having been sampled at the same instant. A delay that is harmless for a slowly changing quantity can distort a comparison of changing signals. The acquisition clock is part of the evidence.

Use Measurement, Units & Engineering Evidence; Electrical Circuits & Network Behaviour; and Electronics, Signals & Devices. This chapter defines its conversion slopes, timing terms and byte conventions. Force-voltage models, reference pairs, clocks, motor parameters and all plotted data are original constructed teaching inputs. They are not hardware selections, wiring instructions, operating limits or qualified calibration records.

Back to the chapter

After reading, you can

Interpret sample timing, channel skew, filtering and data age as parts of the measurement.

01

Name the instant represented by a value

Sampling selects observations at discrete times; quantisation assigns finite digital values to them. The time when the physical input is sampled can differ from the time when a converted result becomes available or reaches a file. A timestamp needs a declared meaning and a relation to the physical event being studied.

A multiplexed system can share one converter across channels, acquiring them in sequence. A simultaneous-sampling arrangement can reduce this interchannel offset, but clock paths and channel delays still require characterisation. The advertised sample rate may refer to each channel or to an aggregate conversion rate; the distinction changes the attainable record.

02

A common start does not ensure a common timebase

Channel skew is a relative timing difference. Latency is elapsed time between an input event and its available result. Jitter is variation in timing from one event to another. A constant delay may be corrected if known, while uncertain or variable delay leaves uncertainty. Filtering and sensor response can add frequency-dependent delay beyond the converter clock.

Two independent clocks can start together and gradually separate. A supplied relative rate mismatch of 20 parts per million accumulates 20×10⁻⁶×100 s=.002 s over 100 s. A common trigger can align a start while leaving this drift. Synchronisation evidence must address the duration and the precision needed for the actual comparison.

A scan row is not necessarily a simultaneous observationCircles and triangles lie on the same 50 Hz waveform but their sample instants differ by 2 ms.Two channels can sample the same waveform at different timesSupplied common input / VActual acquisition time / ms05101520-101Circles: A; triangles: B; B acquired 2 ms later per rowKnown 50 Hz sine; assigning one time to each row creates 36° skew
Known common input sin(2π50t) V, with t in seconds. Channel A times are 0, 5, 10, 15 and 20 ms; B times are 2, 7, 12 and 17 ms. Row-wise sampling delay 0.002 s corresponds to 360×50×0.002=36 degrees. The plot uses actual time; apparent interchannel phase appears only if the acquisition times are incorrectly treated as equal.
03

Keep the input spectrum and the record intact

A finite sampling rate cannot distinguish every possible continuous waveform. For ordinary low-frequency-band acquisition, the input needs a justified band limit and adequate sampling margin. An analogue anti-alias filter suppresses unwanted components before sampling; a later digital filter cannot generally identify and remove a component already folded onto the wanted signal.

Record channel order, actual timing, filter settings, units and configuration. Buffering can decouple acquisition from file writing, but it can also conceal growing delay or overflow unless monitored. Missing samples, repeated stale values and reordered records should remain identifiable. A smooth line drawn through them is a presentation choice, not replacement evidence.

Check an apparent phase difference

The original common signal is sin(2π50t) V. Channel A samples at 0, 5, 10 and 15 ms; channel B at 2, 7, 12 and 17 ms. The channels observe the same waveform, but pairing each row as simultaneous introduces a 2 ms timing error. Its phase equivalent is 360×50×.002=36°.

At the first row, A sees 0 V while B sees sin(.2π)≈.588 V. The figure places both at their actual times so their common origin remains visible. The waveform is supplied exactly for this example; sparse points alone would not establish that it is a unique 50 Hz sine. A timing correction also cannot repair an unknown sensor lag without further evidence.

Try the reasoning

  1. Does the file-write timestamp necessarily identify sample time?

    Show the answer and reasoning

    No. Conversion, transport, buffering and software can separate those instants.

  2. Why can one common trigger leave a long record misaligned?

    Show the answer and reasoning

    Independent sample clocks can drift after the shared start.

  3. Can digital smoothing reliably undo aliasing after acquisition?

    Show the answer and reasoning

    No. Aliased and wanted components may already be indistinguishable in the sampled record.

What to carry forward

Attach every changing measurement to its actual acquisition time and bandwidth.

References

Teaching resources and research supporting this lesson’s explanations and examples.

  1. MT-002 — What the Nyquist Criterion Means to Your Sampled Data System DesignAnalog DevicesTeaching resource · PDFanalog.comRead source
  2. NI-DAQmx Synchronization of PXI Express ModulesNational InstrumentsTeaching resourceni.comRead source